1. Field of the Invention This invention relates to a method for manufacturing a Bi-CMOS Semiconductor Device and more particularly to a fabrication technique for producing a Bi-CMOS device with vertical bipolar NPN and PNP components.
2. Related Art
Bi-CMOS technology (bipolar and CMOS transistors on a single semiconductor substrate) has become an increasingly attractive device technology because it can provide high performance (better than CMOS alone) without high power consumption (much lower than bipolar alone). One the recognized drawbacks in fabricating such Bi-CMOS devices is the increased processing required to produce such high performance CMOS and bioplar components on the same chip. Heretofore, the skill in the art has been to combine the separate processes steps as known for each technology into a combined processing sequence. This has resulted in overly complicated processing plans, which plans are undesirable as they contain excessive processing steps and are time-consuming and costly. Therefore, there has been an ever increasing need for a Bi-CMOS device which can be fabricated with a greater integration of the bipolar and CMOS process steps.
In order to reduce the processing complexity, the invention herein incorporates a structure which was specially developed to be compatible with the bipolar and the CMOS device. With this structure, processing steps can now be shared to simplify the Bi-CMOS fabrication.
As a representative example, a significant reduction in the processing complexity can be achieved by incorporating the following fabrication steps:
(1) forming the reach-through to the subcollector by using steps having other functions; PA0 (2) combining into one mask the threshold adjust/well implants with self-aligned isolation by using a self-aligned removable oxide mask prior to field isolation; PA0 (3) using a resist etch-back scheme to protect against emitter-base punch-through while self-aligning the pedestal and base; and PA0 (4) providing for the removal of the gate oxide at the emitter while maintaining it with the FET without the necessity of using extra mask steps.
In this field some of these process steps have been performed on an individual basis. For example, in U.S. Pat. No. 4,721,686, a reduction in masking steps is taught by performing a boron implant on the surface of an epitaxial layer without masking, and arsenic implant in predetermined locations on the epitaxial layer surface by means of an appropriate mask. to the integrated reduction in masking steps of the present Bi-CMOS fabrication.
In addition, there are other processing techniques which are known in this field for the production of Bi-COMS devices. U.S. Pat. No. 4,484,388 discloses a method for forming a Bi-CMOS structure whereas a different Bi-CMOS device is produced by an unrelated process whcih includes steps to form an emitter self-aligned to the base and form the gate oxide over the emitter.
Another example of related teachings in the fabrication of Bi-CMOS devices is U.S. Pat. No. 4,737,472. This patent discloses a process for the fabrication of Bi-CMOS devices wherein the bipolar device is a self-aligned transistor using polysilicon contacts. This device requires a more complicated process for fabrication and also has a different structure.
A still further teaching in the art of self-aligned polysilicon transistors is seen in the article "Increased Current Gain and Suppression of Peripheral Base Current is Silicided Self-Aligned Narrow Width Polysilicon-Emitter Transistors of an Advanced Bi-CMOS Technology," IEEE Electron Device Letters, Vol. 9, May 1988. Therein the current gain of Bi-CMOS devices is taught to be improved by the introduction of a lightly doped extrinsic base region (LDEB) below the oxide sidewall spacer. However, the incorporation of (LDEB) region is a single process modification without teaching integration of the fabrication of the Bi-CMOS device.
It is, therefore, an object of the present invention to develop a process for fabricating a Bi-CMOS device which process includes common steps for integration of the fabrication of the bipolar and CMOS device.
It is a further object of the present invention to develop a process which is simpler and more efficient in the use of the processing steps in the fabrication of the Bi-CMOS device.
It is a still further object of the present invention to develop a process for fabricating a Bi-CMOS device which includes both a vertical NPN and vertical PNP components.